1. Field of the Invention
The invention relates to a silicon wafer and to a process for producing the silicon wafer which encompasses a heat treatment of the silicon wafer.
2. The Prior Art
The prior art has disclosed silicon wafers which, for various purposes, have layers on their front or back surface. For example, to establish a vertical resistance profile, silicon wafers are provided with an epitaxial layer on their front surface which, at least with respect to a dopant, has a concentration which differs from the remainder of the silicon wafer. The same purpose is also fulfilled by out diffusion of a dopant contained in the wafer as a result of a heat treatment, for example in a hydrogen atmosphere. In particular, layers which act as external getters for various types of impurities, e.g. metals, with which the silicon wafer becomes contaminated during the fabrication of electronic components are produced on the wafer back surface. The layer, which consists, for example, of silicon oxide, silicon nitride or polycrystalline silicon, by means of the lattice mismatch generates a structurally disturbed region which acts as a getter center, i.e. binds impurities.
The silicon wafers are produced from silicon single crystals, which are divided into wafers and are subjected to numerous processing steps in order to obtain the desired surface quality.
Silicon single crystals, which are generally produced using the Czochralski crucible pulling process or using the crucible-free float zone process, have a number of defects. If no special precautions are taken, the defects are also present at the surface of the wafers, where they have an adverse effect on the functioning of the electronic components fabricated thereon.
One significant type of defect is what are known as COPs (crystal originated particles), groups of vacancies which combine to form small voids with sizes of typically between 50 and 150 nm. These defects can be measured using numerous methods. Partial etching of the defects by means of an SC1 solution (NH3/H2O2/H2O) at approximately 85° C. for 20 min followed by light scattering measurement is one possible option for testing for COPs on the wafer surface. Partial etching of the defects by means of a Secco etch for 30 min, removing approximately 30 μm of silicon, followed by counting, also makes it possible to reveal these defects. If the defects which have what is known as a flag are counted, they are referred to as FPDs (flow pattern defects). The result obtained is an FPD density per unit area, which can be converted into a density per unit volume taking account of the material removed during the preparatory etch. The same defects can also be measured by IR-LST (infra-red light scattering tomography), in which an Nd-YAG laser beam is scattered at the defects in the silicon wafer and the scattered light is detected at an angle of 90° to the laser beam. These defects are referred to as LSTD defects after their measurement method.
Numerous component parameters are adversely affected by the COPs when components are being fabricated on the semiconductor wafer. Therefore, it is necessary for these defects to be removed at least in the layer of a silicon wafer that is active in terms of the components.
European Patent EP 973 190 A2 teaches subjecting a single-crystal silicon wafer which, on its back surface, bears an external getter layer of polycrystalline silicon to a heat treatment at a temperature between 1150 and 1350° C. in a hydrogen-containing atmosphere in order to remove the COPs at the surface of the silicon wafer.
U.S. Pat. No. 6,423,615 teaches that the dopant concentration in a layer close to the surface is altered by means of a heat treatment in a hydrogen-containing atmosphere, so that a vertical resistance profile is generated. A layer of this type with an altered dopant concentration at the front surface of the silicon wafer is required for many component processes.
It is also known that by means of an epitaxial deposition on the front surface of the silicon wafer, it is possible to generate a layer which has a different dopant concentration and is free of COPs.
Therefore, the prior art has disclosed silicon wafers which, on the front or back surface, bear at least one of the abovementioned layers and the surface of which, at least on the front surface, is substantially free of COPs. The remainder of the silicon wafer, known as the bulk, however, is not free of COPs. This is disadvantageous in particular if components which require a particularly deep COP-free layer at the surface, for example in the case of components in which what is known as the deep trench technologies are employed, are fabricated on the silicon wafer. The maximum depth of the component has been restricted to the thickness of the COP-free layer. Moreover, the growth of a thick epitaxial layer which is suitable for deep trench technology is very time-consuming and therefore expensive.